1. Field of the Invention
The present invention relates to a ring oscillator for use in a voltage-controlled oscillator for a PLL circuit.
2. Description of the Background Art
FIG. 19 is a circuit diagram showing the internal construction of a conventional voltage-controlled ring oscillator. Referring to FIG. 19, five inverters Gi (i=1 to 5), or G1 to G5, each basically comprised of a CMOS structure including a PMOS transistor QPi and an NMOS transistor QNi are connected in series to form an inverter group. The output of the last inverter G5 is outputted in the form of an oscillation signal S2 from an output terminal 2 to the exterior and is fed back to the input of the first inverter G1 to form a five-stage loop.
In each inverter Gi, the source of the PMOS transistor QPi is connected to a power supply VDD through a PMOS transistor TPi and the source of the NMOS transistor QNi is grounded through an NMOS transistor TNi.
A PMOS transistor 21 and an NMOS transistor 31 are connected in series between the power supply VDD and ground, and the PMOS transistor 21 is current-mirror connected to the PMOS transistors TP1 to TP5. The gate of the NMOS transistor 31 is connected to a voltage control terminal 1 and is commonly connected to the NMOS transistors TN1 to TN5. A control voltage CV is applied to the voltage control terminal 1.
In this manner, an odd number of (five) inverters are connected in a loop to provide the oscillation signal S2 oscillating at a predetermined oscillation frequency f at the output terminal 2 connected to the output of the inverter G5. The oscillation frequency f of the oscillation signal S2 is determined by the number of inverters forming the loop and the signal propagation delay time of the individual inverters.
The amount of current flowing in the NMOS transistor 31 is controlled by the magnitude of the control voltage CV applied to the voltage control terminal 1, thereby to determine a control current 11 flowing in the PMOS transistor 21.
Consequently, the gates of the NMOS transistors TN1 to TN5 are also connected to the voltage control terminal 1, and the PMOS transistors TP1 to TP5 form current mirror circuits with the PMOS transistor 21. Thus, the source current of each inverter Gi is controlled so that the amount of the source current is proportional to the control current I1.
That is, the control voltage CV applied to the voltage control terminal 1 controls the source current of each inverter Gi, thereby to change the signal propagation delay time of each inverter Gi to change the oscillation frequency f of the oscillation signal S2.
The ring oscillator as above constructed is used as a clock source 44 for generating a clock CK for operating circuits 41 to 43 formed in an IC chip 10 as shown in FIG. 20. The ring oscillator is also used as a VCO 53 for a PLL circuit including a phase comparator 51, a low-pass filter 52 and the VCO 53 for locking the phase of an output signal OUT into that of a reference signal F0 as shown in FIG. 21.
In the conventional voltage-controlled ring oscillator as above constructed, the oscillation frequency f of the oscillation signal S2 has been changed by the control voltage CV applied to the voltage control terminal 1.
However, since the conventional ring oscillator includes a fixed number of inverters connected in a loop, changes of the oscillation frequency f of the oscillation signal S2 depend only upon control of the signal propagation delay time of the individual inverters Gi by the control voltage CV.
Unfortunately, the control range of the signal propagation delay time of the individual inverters Gi by the control voltage CV is limited to a level which prevents the malfunction of the inverters. Accordingly, the frequency band of the oscillation frequency f of the oscillation signal S2 which can be varied by the control voltage CV is limited to that of a narrow width.
Furthermore, since decrease in voltage value of the power supply VDD decreases the source current of the inverters, the frequency band of the oscillation frequency f which can be controlled by the control voltage CV is further reduced if the conventional voltage-controlled ring oscillator is operated by the power supply VDD having a low voltage. It has therefore been impossible to output the oscillation signal S2 having the same oscillation frequency in the cases of the power supply voltages of 5 V and 3 V under control of the control voltage CV of the conventional ring oscillator.